339 lines
3.9 KiB
Scheme
339 lines
3.9 KiB
Scheme
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(comment) @comment
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; Keywords
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[
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; vhdl 08
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"abs"
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"access"
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"after"
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"alias"
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"all"
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"and"
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"architecture"
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"array"
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"assert"
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"attribute"
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"begin"
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"block"
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"body"
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"buffer"
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"bus"
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"case"
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"component"
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"configuration"
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"constant"
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"disconnect"
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"downto"
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"else"
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"elsif"
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"end"
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"entity"
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"exit"
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"file"
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"for"
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"function"
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"generic"
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"group"
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"guarded"
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"if"
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"impure"
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"in"
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"inertial"
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"inout"
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"is"
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"label"
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"library"
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"linkage"
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"literal"
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"loop"
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"map"
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"mod"
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"nand"
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"new"
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"next"
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"nor"
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"not"
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"null"
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"of"
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"on"
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"open"
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"or"
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"others"
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"out"
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"package"
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"port"
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"postponed"
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"procedure"
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"process"
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"protected"
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"pure"
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"range"
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"record"
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"register"
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"reject"
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"rem"
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"report"
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"return"
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"rol"
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"ror"
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"select"
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"severity"
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"shared"
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"signal"
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"sla"
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"sll"
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"sra"
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"srl"
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"subtype"
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"then"
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"to"
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"transport"
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"type"
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"unaffected"
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"units"
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"until"
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"use"
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"variable"
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"wait"
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"when"
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"while"
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"with"
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"xnor"
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"xor"
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; vhdl 08
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"context"
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"force"
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"property"
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"release"
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"sequence"
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] @keyword
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[
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; vhdl 02
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"boolean"
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"bit"
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"bit_vector"
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;"character"
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;"severity_level"
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;"integer"
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;"real"
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;"time"
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;"natural"
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;"positive"
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"string"
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;"line"
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;"text"
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;"side"
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;"unsigned"
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;"signed"
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;"delay_length"
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;"file_open_kind"
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;"file_open_status"
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;"std_logic"
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;"std_logic_vector"
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;"std_ulogic"
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;"std_ulogic_vector"
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; vhdl 08
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;"boolean_vector"
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;"integer_vector"
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;"real_vector"
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;"time_vector"
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; math types
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;"complex"
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;"complex_polar"
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;"positive_real"
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;"principal_value"
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] @type.builtin
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[
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; vhdl 02
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"base"
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"left"
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"right"
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"high"
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"low"
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"pos"
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"val"
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"succ"
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"pred"
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"leftof"
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"rightof"
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"range"
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"reverse_range"
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"length"
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"delayed"
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"stable"
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"quiet"
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"transaction"
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"event"
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"active"
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"last_event"
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"last_active"
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"last_value"
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"driving"
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"driving_value"
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"ascending"
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"value"
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"image"
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"simple_name"
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"instance_name"
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"path_name"
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;"foreign"
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; vhdl 08
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"instance_name"
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"path_name"
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] @attribute
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;[
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; vhdl 02
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;"now"
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;"resolved"
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;"rising_edge"
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;"falling_edge"
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;"read"
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;"readline"
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;"hread"
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;"oread"
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;"write"
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;"writeline"
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;"hwrite"
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;"owrite"
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;"endfile"
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;"resize"
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;"is_X"
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;"std_match"
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;"shift_left"
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;"shift_right"
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;"rotate_left"
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;"rotate_right"
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;"to_unsigned"
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;"to_signed"
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;"to_integer"
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;"to_stdLogicVector"
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;"to_stdULogic"
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;"to_stdULogicVector"
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;"to_bit"
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;"to_bitVector"
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;"to_X01"
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;"to_X01Z"
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;"to_UX01"
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;"to_01"
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;"conv_unsigned"
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;"conv_signed"
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;"conv_integer"
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;"conv_std_logic_vector"
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;"shl"
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;"shr"
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;"ext"
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;"sxt"
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;"deallocate"
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; vhdl 08
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;"finish"
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;"flush"
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;"justify"
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;"maximum"
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;"minimum"
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;"resolution_limit"
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;"stop"
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;"swrite"
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;"tee"
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;"to_binarystring"
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;"to_bstring"
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;"to_hexstring"
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;"to_hstring"
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;"to_octalstring"
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;"to_ostring"
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;"to_string"
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; vhdl math
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;"arccos"
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;"arccosh"
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;"arcsin"
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;"arcsinh"
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;"arctan"
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;"arctanh"
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;"arg"
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;"cbrt"
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;"ceil"
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;"cmplx"
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;"complex_to_polar"
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;"conj"
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;"cos"
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;"cosh"
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;"exp"
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;"floor"
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;"get_principal_value"
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;"log"
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;"log10"
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;"log2"
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;"polar_to_complex"
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;"realmax"
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;"realmin"
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;"round"
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;"sign"
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;"sin"
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;"sinh"
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;"sqrt"
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;"tan"
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;"tanh"
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;"trunc"
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;"uniform"
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;] @function.builtin
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; Operators
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[
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"+"
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"-"
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"*"
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"/"
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"**"
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"abs"
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"not"
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"mod"
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"rem"
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"&"
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"sll"
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"srl"
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"sla"
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"sra"
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"rol"
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"ror"
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"="
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"/="
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"?="
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"?/="
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"?<"
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"?<="
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"?>"
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"?>="
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"<"
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"<="
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">"
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">="
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"and"
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"or"
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"nand"
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"nor"
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"xor"
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"xnor"
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":="
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"<="
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"??"
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] @operator
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[
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";"
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","
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] @punctuation.delimiter
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[
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"("
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")"
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"'"
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] @punctuation.bracket
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(full_type_declaration "type" name: (identifier) @type)
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(signal_declaration "signal" (identifier_list) @variable)
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(variable_declaration "variable" (identifier_list) @variable)
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(constant_declaration "constant" (identifier_list) @variable)
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