7613f31c6b
* update gitea.com/go-chi/binding
* update github.com/blevesearch/bleve/v2
* update github.com/caddyserver/certmagic
* update github.com/go-git/go-git/v5
* update github.com/lafriks/xormstore
* update github.com/yuin/goldmark
* Revert "update gitea.com/go-chi/binding"
This reverts commit dea2f292b1.
1068 lines
31 KiB
Go
Vendored
1068 lines
31 KiB
Go
Vendored
// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file.
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// Package cpuid provides information about the CPU running the current program.
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//
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// CPU features are detected on startup, and kept for fast access through the life of the application.
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// Currently x86 / x64 (AMD64) as well as arm64 is supported.
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//
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// You can access the CPU information by accessing the shared CPU variable of the cpuid library.
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//
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// Package home: https://github.com/klauspost/cpuid
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package cpuid
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import (
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"flag"
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"fmt"
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"math"
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"os"
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"runtime"
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"strings"
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)
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// AMD refererence: https://www.amd.com/system/files/TechDocs/25481.pdf
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// and Processor Programming Reference (PPR)
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// Vendor is a representation of a CPU vendor.
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type Vendor int
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const (
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VendorUnknown Vendor = iota
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Intel
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AMD
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VIA
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Transmeta
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NSC
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KVM // Kernel-based Virtual Machine
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MSVM // Microsoft Hyper-V or Windows Virtual PC
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VMware
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XenHVM
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Bhyve
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Hygon
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SiS
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RDC
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Ampere
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ARM
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Broadcom
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Cavium
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DEC
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Fujitsu
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Infineon
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Motorola
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NVIDIA
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AMCC
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Qualcomm
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Marvell
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lastVendor
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)
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//go:generate stringer -type=FeatureID,Vendor
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// FeatureID is the ID of a specific cpu feature.
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type FeatureID int
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const (
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// Keep index -1 as unknown
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UNKNOWN = -1
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// Add features
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ADX FeatureID = iota // Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
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AESNI // Advanced Encryption Standard New Instructions
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AMD3DNOW // AMD 3DNOW
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AMD3DNOWEXT // AMD 3DNowExt
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AMXBF16 // Tile computational operations on BFLOAT16 numbers
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AMXINT8 // Tile computational operations on 8-bit integers
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AMXTILE // Tile architecture
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AVX // AVX functions
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AVX2 // AVX2 functions
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AVX512BF16 // AVX-512 BFLOAT16 Instructions
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AVX512BITALG // AVX-512 Bit Algorithms
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AVX512BW // AVX-512 Byte and Word Instructions
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AVX512CD // AVX-512 Conflict Detection Instructions
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AVX512DQ // AVX-512 Doubleword and Quadword Instructions
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AVX512ER // AVX-512 Exponential and Reciprocal Instructions
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AVX512F // AVX-512 Foundation
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AVX512IFMA // AVX-512 Integer Fused Multiply-Add Instructions
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AVX512PF // AVX-512 Prefetch Instructions
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AVX512VBMI // AVX-512 Vector Bit Manipulation Instructions
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AVX512VBMI2 // AVX-512 Vector Bit Manipulation Instructions, Version 2
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AVX512VL // AVX-512 Vector Length Extensions
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AVX512VNNI // AVX-512 Vector Neural Network Instructions
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AVX512VP2INTERSECT // AVX-512 Intersect for D/Q
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AVX512VPOPCNTDQ // AVX-512 Vector Population Count Doubleword and Quadword
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AVXSLOW // Indicates the CPU performs 2 128 bit operations instead of one.
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BMI1 // Bit Manipulation Instruction Set 1
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BMI2 // Bit Manipulation Instruction Set 2
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CLDEMOTE // Cache Line Demote
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CLMUL // Carry-less Multiplication
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CLZERO // CLZERO instruction supported
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CMOV // i686 CMOV
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CPBOOST // Core Performance Boost
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CX16 // CMPXCHG16B Instruction
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ENQCMD // Enqueue Command
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ERMS // Enhanced REP MOVSB/STOSB
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F16C // Half-precision floating-point conversion
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FMA3 // Intel FMA 3. Does not imply AVX.
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FMA4 // Bulldozer FMA4 functions
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GFNI // Galois Field New Instructions
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HLE // Hardware Lock Elision
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HTT // Hyperthreading (enabled)
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HWA // Hardware assert supported. Indicates support for MSRC001_10
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HYPERVISOR // This bit has been reserved by Intel & AMD for use by hypervisors
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IBPB // Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Predictor Barrier (IBPB)
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IBS // Instruction Based Sampling (AMD)
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IBSBRNTRGT // Instruction Based Sampling Feature (AMD)
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IBSFETCHSAM // Instruction Based Sampling Feature (AMD)
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IBSFFV // Instruction Based Sampling Feature (AMD)
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IBSOPCNT // Instruction Based Sampling Feature (AMD)
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IBSOPCNTEXT // Instruction Based Sampling Feature (AMD)
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IBSOPSAM // Instruction Based Sampling Feature (AMD)
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IBSRDWROPCNT // Instruction Based Sampling Feature (AMD)
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IBSRIPINVALIDCHK // Instruction Based Sampling Feature (AMD)
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INT_WBINVD // WBINVD/WBNOINVD are interruptible.
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INVLPGB // NVLPGB and TLBSYNC instruction supported
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LZCNT // LZCNT instruction
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MCAOVERFLOW // MCA overflow recovery support.
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MCOMMIT // MCOMMIT instruction supported
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MMX // standard MMX
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MMXEXT // SSE integer functions or AMD MMX ext
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MOVDIR64B // Move 64 Bytes as Direct Store
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MOVDIRI // Move Doubleword as Direct Store
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MPX // Intel MPX (Memory Protection Extensions)
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MSRIRC // Instruction Retired Counter MSR available
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NX // NX (No-Execute) bit
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POPCNT // POPCNT instruction
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RDPRU // RDPRU instruction supported
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RDRAND // RDRAND instruction is available
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RDSEED // RDSEED instruction is available
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RDTSCP // RDTSCP Instruction
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RTM // Restricted Transactional Memory
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RTM_ALWAYS_ABORT // Indicates that the loaded microcode is forcing RTM abort.
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SERIALIZE // Serialize Instruction Execution
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SGX // Software Guard Extensions
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SGXLC // Software Guard Extensions Launch Control
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SHA // Intel SHA Extensions
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SSE // SSE functions
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SSE2 // P4 SSE functions
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SSE3 // Prescott SSE3 functions
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SSE4 // Penryn SSE4.1 functions
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SSE42 // Nehalem SSE4.2 functions
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SSE4A // AMD Barcelona microarchitecture SSE4a instructions
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SSSE3 // Conroe SSSE3 functions
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STIBP // Single Thread Indirect Branch Predictors
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SUCCOR // Software uncorrectable error containment and recovery capability.
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TBM // AMD Trailing Bit Manipulation
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TSXLDTRK // Intel TSX Suspend Load Address Tracking
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VAES // Vector AES
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VMX // Virtual Machine Extensions
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VPCLMULQDQ // Carry-Less Multiplication Quadword
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WAITPKG // TPAUSE, UMONITOR, UMWAIT
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WBNOINVD // Write Back and Do Not Invalidate Cache
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XOP // Bulldozer XOP functions
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// ARM features:
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AESARM // AES instructions
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ARMCPUID // Some CPU ID registers readable at user-level
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ASIMD // Advanced SIMD
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ASIMDDP // SIMD Dot Product
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ASIMDHP // Advanced SIMD half-precision floating point
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ASIMDRDM // Rounding Double Multiply Accumulate/Subtract (SQRDMLAH/SQRDMLSH)
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ATOMICS // Large System Extensions (LSE)
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CRC32 // CRC32/CRC32C instructions
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DCPOP // Data cache clean to Point of Persistence (DC CVAP)
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EVTSTRM // Generic timer
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FCMA // Floatin point complex number addition and multiplication
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FP // Single-precision and double-precision floating point
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FPHP // Half-precision floating point
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GPA // Generic Pointer Authentication
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JSCVT // Javascript-style double->int convert (FJCVTZS)
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LRCPC // Weaker release consistency (LDAPR, etc)
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PMULL // Polynomial Multiply instructions (PMULL/PMULL2)
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SHA1 // SHA-1 instructions (SHA1C, etc)
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SHA2 // SHA-2 instructions (SHA256H, etc)
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SHA3 // SHA-3 instructions (EOR3, RAXI, XAR, BCAX)
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SHA512 // SHA512 instructions
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SM3 // SM3 instructions
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SM4 // SM4 instructions
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SVE // Scalable Vector Extension
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// Keep it last. It automatically defines the size of []flagSet
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lastID
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firstID FeatureID = UNKNOWN + 1
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)
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// CPUInfo contains information about the detected system CPU.
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type CPUInfo struct {
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BrandName string // Brand name reported by the CPU
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VendorID Vendor // Comparable CPU vendor ID
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VendorString string // Raw vendor string.
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featureSet flagSet // Features of the CPU
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PhysicalCores int // Number of physical processor cores in your CPU. Will be 0 if undetectable.
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ThreadsPerCore int // Number of threads per physical core. Will be 1 if undetectable.
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LogicalCores int // Number of physical cores times threads that can run on each core through the use of hyperthreading. Will be 0 if undetectable.
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Family int // CPU family number
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Model int // CPU model number
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CacheLine int // Cache line size in bytes. Will be 0 if undetectable.
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Hz int64 // Clock speed, if known, 0 otherwise. Will attempt to contain base clock speed.
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BoostFreq int64 // Max clock speed, if known, 0 otherwise
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Cache struct {
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L1I int // L1 Instruction Cache (per core or shared). Will be -1 if undetected
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L1D int // L1 Data Cache (per core or shared). Will be -1 if undetected
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L2 int // L2 Cache (per core or shared). Will be -1 if undetected
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L3 int // L3 Cache (per core, per ccx or shared). Will be -1 if undetected
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}
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SGX SGXSupport
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maxFunc uint32
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maxExFunc uint32
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}
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var cpuid func(op uint32) (eax, ebx, ecx, edx uint32)
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var cpuidex func(op, op2 uint32) (eax, ebx, ecx, edx uint32)
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var xgetbv func(index uint32) (eax, edx uint32)
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var rdtscpAsm func() (eax, ebx, ecx, edx uint32)
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var darwinHasAVX512 = func() bool { return false }
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// CPU contains information about the CPU as detected on startup,
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// or when Detect last was called.
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//
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// Use this as the primary entry point to you data.
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var CPU CPUInfo
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func init() {
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initCPU()
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Detect()
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}
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// Detect will re-detect current CPU info.
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// This will replace the content of the exported CPU variable.
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//
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// Unless you expect the CPU to change while you are running your program
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// you should not need to call this function.
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// If you call this, you must ensure that no other goroutine is accessing the
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// exported CPU variable.
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func Detect() {
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// Set defaults
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CPU.ThreadsPerCore = 1
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CPU.Cache.L1I = -1
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CPU.Cache.L1D = -1
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CPU.Cache.L2 = -1
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CPU.Cache.L3 = -1
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safe := true
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if detectArmFlag != nil {
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safe = !*detectArmFlag
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}
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addInfo(&CPU, safe)
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if displayFeats != nil && *displayFeats {
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fmt.Println("cpu features:", strings.Join(CPU.FeatureSet(), ","))
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// Exit with non-zero so tests will print value.
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os.Exit(1)
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}
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if disableFlag != nil {
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s := strings.Split(*disableFlag, ",")
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for _, feat := range s {
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feat := ParseFeature(strings.TrimSpace(feat))
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if feat != UNKNOWN {
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CPU.featureSet.unset(feat)
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}
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}
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}
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}
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// DetectARM will detect ARM64 features.
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// This is NOT done automatically since it can potentially crash
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// if the OS does not handle the command.
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// If in the future this can be done safely this function may not
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// do anything.
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func DetectARM() {
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addInfo(&CPU, false)
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}
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var detectArmFlag *bool
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var displayFeats *bool
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var disableFlag *string
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// Flags will enable flags.
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// This must be called *before* flag.Parse AND
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// Detect must be called after the flags have been parsed.
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// Note that this means that any detection used in init() functions
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// will not contain these flags.
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func Flags() {
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disableFlag = flag.String("cpu.disable", "", "disable cpu features; comma separated list")
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displayFeats = flag.Bool("cpu.features", false, "lists cpu features and exits")
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detectArmFlag = flag.Bool("cpu.arm", false, "allow ARM features to be detected; can potentially crash")
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}
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// Supports returns whether the CPU supports all of the requested features.
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func (c CPUInfo) Supports(ids ...FeatureID) bool {
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for _, id := range ids {
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if !c.featureSet.inSet(id) {
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return false
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}
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}
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return true
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}
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// Has allows for checking a single feature.
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// Should be inlined by the compiler.
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func (c CPUInfo) Has(id FeatureID) bool {
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return c.featureSet.inSet(id)
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}
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// Disable will disable one or several features.
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func (c *CPUInfo) Disable(ids ...FeatureID) bool {
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for _, id := range ids {
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c.featureSet.unset(id)
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}
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return true
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}
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// Enable will disable one or several features even if they were undetected.
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// This is of course not recommended for obvious reasons.
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func (c *CPUInfo) Enable(ids ...FeatureID) bool {
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for _, id := range ids {
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c.featureSet.set(id)
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}
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return true
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}
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// IsVendor returns true if vendor is recognized as Intel
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func (c CPUInfo) IsVendor(v Vendor) bool {
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return c.VendorID == v
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}
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func (c CPUInfo) FeatureSet() []string {
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s := make([]string, 0)
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for _, f := range c.featureSet.Strings() {
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s = append(s, f)
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}
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return s
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}
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// RTCounter returns the 64-bit time-stamp counter
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// Uses the RDTSCP instruction. The value 0 is returned
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// if the CPU does not support the instruction.
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func (c CPUInfo) RTCounter() uint64 {
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if !c.Supports(RDTSCP) {
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return 0
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}
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a, _, _, d := rdtscpAsm()
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return uint64(a) | (uint64(d) << 32)
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}
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// Ia32TscAux returns the IA32_TSC_AUX part of the RDTSCP.
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// This variable is OS dependent, but on Linux contains information
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// about the current cpu/core the code is running on.
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// If the RDTSCP instruction isn't supported on the CPU, the value 0 is returned.
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func (c CPUInfo) Ia32TscAux() uint32 {
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if !c.Supports(RDTSCP) {
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return 0
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}
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_, _, ecx, _ := rdtscpAsm()
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return ecx
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}
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// LogicalCPU will return the Logical CPU the code is currently executing on.
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// This is likely to change when the OS re-schedules the running thread
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// to another CPU.
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// If the current core cannot be detected, -1 will be returned.
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func (c CPUInfo) LogicalCPU() int {
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if c.maxFunc < 1 {
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return -1
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}
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_, ebx, _, _ := cpuid(1)
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return int(ebx >> 24)
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}
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// frequencies tries to compute the clock speed of the CPU. If leaf 15 is
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// supported, use it, otherwise parse the brand string. Yes, really.
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func (c *CPUInfo) frequencies() {
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c.Hz, c.BoostFreq = 0, 0
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mfi := maxFunctionID()
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if mfi >= 0x15 {
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eax, ebx, ecx, _ := cpuid(0x15)
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if eax != 0 && ebx != 0 && ecx != 0 {
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c.Hz = (int64(ecx) * int64(ebx)) / int64(eax)
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}
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}
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if mfi >= 0x16 {
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a, b, _, _ := cpuid(0x16)
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// Base...
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if a&0xffff > 0 {
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c.Hz = int64(a&0xffff) * 1_000_000
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}
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// Boost...
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if b&0xffff > 0 {
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c.BoostFreq = int64(b&0xffff) * 1_000_000
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}
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}
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if c.Hz > 0 {
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return
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}
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// computeHz determines the official rated speed of a CPU from its brand
|
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// string. This insanity is *actually the official documented way to do
|
||
// this according to Intel*, prior to leaf 0x15 existing. The official
|
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// documentation only shows this working for exactly `x.xx` or `xxxx`
|
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// cases, e.g., `2.50GHz` or `1300MHz`; this parser will accept other
|
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// sizes.
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model := c.BrandName
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hz := strings.LastIndex(model, "Hz")
|
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if hz < 3 {
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return
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}
|
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var multiplier int64
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||
switch model[hz-1] {
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case 'M':
|
||
multiplier = 1000 * 1000
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case 'G':
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||
multiplier = 1000 * 1000 * 1000
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||
case 'T':
|
||
multiplier = 1000 * 1000 * 1000 * 1000
|
||
}
|
||
if multiplier == 0 {
|
||
return
|
||
}
|
||
freq := int64(0)
|
||
divisor := int64(0)
|
||
decimalShift := int64(1)
|
||
var i int
|
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for i = hz - 2; i >= 0 && model[i] != ' '; i-- {
|
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if model[i] >= '0' && model[i] <= '9' {
|
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freq += int64(model[i]-'0') * decimalShift
|
||
decimalShift *= 10
|
||
} else if model[i] == '.' {
|
||
if divisor != 0 {
|
||
return
|
||
}
|
||
divisor = decimalShift
|
||
} else {
|
||
return
|
||
}
|
||
}
|
||
// we didn't find a space
|
||
if i < 0 {
|
||
return
|
||
}
|
||
if divisor != 0 {
|
||
c.Hz = (freq * multiplier) / divisor
|
||
return
|
||
}
|
||
c.Hz = freq * multiplier
|
||
}
|
||
|
||
// VM Will return true if the cpu id indicates we are in
|
||
// a virtual machine.
|
||
func (c CPUInfo) VM() bool {
|
||
return CPU.featureSet.inSet(HYPERVISOR)
|
||
}
|
||
|
||
// flags contains detected cpu features and characteristics
|
||
type flags uint64
|
||
|
||
// log2(bits_in_uint64)
|
||
const flagBitsLog2 = 6
|
||
const flagBits = 1 << flagBitsLog2
|
||
const flagMask = flagBits - 1
|
||
|
||
// flagSet contains detected cpu features and characteristics in an array of flags
|
||
type flagSet [(lastID + flagMask) / flagBits]flags
|
||
|
||
func (s flagSet) inSet(feat FeatureID) bool {
|
||
return s[feat>>flagBitsLog2]&(1<<(feat&flagMask)) != 0
|
||
}
|
||
|
||
func (s *flagSet) set(feat FeatureID) {
|
||
s[feat>>flagBitsLog2] |= 1 << (feat & flagMask)
|
||
}
|
||
|
||
// setIf will set a feature if boolean is true.
|
||
func (s *flagSet) setIf(cond bool, features ...FeatureID) {
|
||
if cond {
|
||
for _, offset := range features {
|
||
s[offset>>flagBitsLog2] |= 1 << (offset & flagMask)
|
||
}
|
||
}
|
||
}
|
||
|
||
func (s *flagSet) unset(offset FeatureID) {
|
||
bit := flags(1 << (offset & flagMask))
|
||
s[offset>>flagBitsLog2] = s[offset>>flagBitsLog2] & ^bit
|
||
}
|
||
|
||
// or with another flagset.
|
||
func (s *flagSet) or(other flagSet) {
|
||
for i, v := range other[:] {
|
||
s[i] |= v
|
||
}
|
||
}
|
||
|
||
// ParseFeature will parse the string and return the ID of the matching feature.
|
||
// Will return UNKNOWN if not found.
|
||
func ParseFeature(s string) FeatureID {
|
||
s = strings.ToUpper(s)
|
||
for i := firstID; i < lastID; i++ {
|
||
if i.String() == s {
|
||
return i
|
||
}
|
||
}
|
||
return UNKNOWN
|
||
}
|
||
|
||
// Strings returns an array of the detected features for FlagsSet.
|
||
func (s flagSet) Strings() []string {
|
||
if len(s) == 0 {
|
||
return []string{""}
|
||
}
|
||
r := make([]string, 0)
|
||
for i := firstID; i < lastID; i++ {
|
||
if s.inSet(i) {
|
||
r = append(r, i.String())
|
||
}
|
||
}
|
||
return r
|
||
}
|
||
|
||
func maxExtendedFunction() uint32 {
|
||
eax, _, _, _ := cpuid(0x80000000)
|
||
return eax
|
||
}
|
||
|
||
func maxFunctionID() uint32 {
|
||
a, _, _, _ := cpuid(0)
|
||
return a
|
||
}
|
||
|
||
func brandName() string {
|
||
if maxExtendedFunction() >= 0x80000004 {
|
||
v := make([]uint32, 0, 48)
|
||
for i := uint32(0); i < 3; i++ {
|
||
a, b, c, d := cpuid(0x80000002 + i)
|
||
v = append(v, a, b, c, d)
|
||
}
|
||
return strings.Trim(string(valAsString(v...)), " ")
|
||
}
|
||
return "unknown"
|
||
}
|
||
|
||
func threadsPerCore() int {
|
||
mfi := maxFunctionID()
|
||
vend, _ := vendorID()
|
||
|
||
if mfi < 0x4 || (vend != Intel && vend != AMD) {
|
||
return 1
|
||
}
|
||
|
||
if mfi < 0xb {
|
||
if vend != Intel {
|
||
return 1
|
||
}
|
||
_, b, _, d := cpuid(1)
|
||
if (d & (1 << 28)) != 0 {
|
||
// v will contain logical core count
|
||
v := (b >> 16) & 255
|
||
if v > 1 {
|
||
a4, _, _, _ := cpuid(4)
|
||
// physical cores
|
||
v2 := (a4 >> 26) + 1
|
||
if v2 > 0 {
|
||
return int(v) / int(v2)
|
||
}
|
||
}
|
||
}
|
||
return 1
|
||
}
|
||
_, b, _, _ := cpuidex(0xb, 0)
|
||
if b&0xffff == 0 {
|
||
if vend == AMD {
|
||
// Workaround for AMD returning 0, assume 2 if >= Zen 2
|
||
// It will be more correct than not.
|
||
fam, _ := familyModel()
|
||
_, _, _, d := cpuid(1)
|
||
if (d&(1<<28)) != 0 && fam >= 23 {
|
||
return 2
|
||
}
|
||
}
|
||
return 1
|
||
}
|
||
return int(b & 0xffff)
|
||
}
|
||
|
||
func logicalCores() int {
|
||
mfi := maxFunctionID()
|
||
v, _ := vendorID()
|
||
switch v {
|
||
case Intel:
|
||
// Use this on old Intel processors
|
||
if mfi < 0xb {
|
||
if mfi < 1 {
|
||
return 0
|
||
}
|
||
// CPUID.1:EBX[23:16] represents the maximum number of addressable IDs (initial APIC ID)
|
||
// that can be assigned to logical processors in a physical package.
|
||
// The value may not be the same as the number of logical processors that are present in the hardware of a physical package.
|
||
_, ebx, _, _ := cpuid(1)
|
||
logical := (ebx >> 16) & 0xff
|
||
return int(logical)
|
||
}
|
||
_, b, _, _ := cpuidex(0xb, 1)
|
||
return int(b & 0xffff)
|
||
case AMD, Hygon:
|
||
_, b, _, _ := cpuid(1)
|
||
return int((b >> 16) & 0xff)
|
||
default:
|
||
return 0
|
||
}
|
||
}
|
||
|
||
func familyModel() (int, int) {
|
||
if maxFunctionID() < 0x1 {
|
||
return 0, 0
|
||
}
|
||
eax, _, _, _ := cpuid(1)
|
||
family := ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff)
|
||
model := ((eax >> 4) & 0xf) + ((eax >> 12) & 0xf0)
|
||
return int(family), int(model)
|
||
}
|
||
|
||
func physicalCores() int {
|
||
v, _ := vendorID()
|
||
switch v {
|
||
case Intel:
|
||
return logicalCores() / threadsPerCore()
|
||
case AMD, Hygon:
|
||
lc := logicalCores()
|
||
tpc := threadsPerCore()
|
||
if lc > 0 && tpc > 0 {
|
||
return lc / tpc
|
||
}
|
||
|
||
// The following is inaccurate on AMD EPYC 7742 64-Core Processor
|
||
if maxExtendedFunction() >= 0x80000008 {
|
||
_, _, c, _ := cpuid(0x80000008)
|
||
if c&0xff > 0 {
|
||
return int(c&0xff) + 1
|
||
}
|
||
}
|
||
}
|
||
return 0
|
||
}
|
||
|
||
// Except from http://en.wikipedia.org/wiki/CPUID#EAX.3D0:_Get_vendor_ID
|
||
var vendorMapping = map[string]Vendor{
|
||
"AMDisbetter!": AMD,
|
||
"AuthenticAMD": AMD,
|
||
"CentaurHauls": VIA,
|
||
"GenuineIntel": Intel,
|
||
"TransmetaCPU": Transmeta,
|
||
"GenuineTMx86": Transmeta,
|
||
"Geode by NSC": NSC,
|
||
"VIA VIA VIA ": VIA,
|
||
"KVMKVMKVMKVM": KVM,
|
||
"Microsoft Hv": MSVM,
|
||
"VMwareVMware": VMware,
|
||
"XenVMMXenVMM": XenHVM,
|
||
"bhyve bhyve ": Bhyve,
|
||
"HygonGenuine": Hygon,
|
||
"Vortex86 SoC": SiS,
|
||
"SiS SiS SiS ": SiS,
|
||
"RiseRiseRise": SiS,
|
||
"Genuine RDC": RDC,
|
||
}
|
||
|
||
func vendorID() (Vendor, string) {
|
||
_, b, c, d := cpuid(0)
|
||
v := string(valAsString(b, d, c))
|
||
vend, ok := vendorMapping[v]
|
||
if !ok {
|
||
return VendorUnknown, v
|
||
}
|
||
return vend, v
|
||
}
|
||
|
||
func cacheLine() int {
|
||
if maxFunctionID() < 0x1 {
|
||
return 0
|
||
}
|
||
|
||
_, ebx, _, _ := cpuid(1)
|
||
cache := (ebx & 0xff00) >> 5 // cflush size
|
||
if cache == 0 && maxExtendedFunction() >= 0x80000006 {
|
||
_, _, ecx, _ := cpuid(0x80000006)
|
||
cache = ecx & 0xff // cacheline size
|
||
}
|
||
// TODO: Read from Cache and TLB Information
|
||
return int(cache)
|
||
}
|
||
|
||
func (c *CPUInfo) cacheSize() {
|
||
c.Cache.L1D = -1
|
||
c.Cache.L1I = -1
|
||
c.Cache.L2 = -1
|
||
c.Cache.L3 = -1
|
||
vendor, _ := vendorID()
|
||
switch vendor {
|
||
case Intel:
|
||
if maxFunctionID() < 4 {
|
||
return
|
||
}
|
||
for i := uint32(0); ; i++ {
|
||
eax, ebx, ecx, _ := cpuidex(4, i)
|
||
cacheType := eax & 15
|
||
if cacheType == 0 {
|
||
break
|
||
}
|
||
cacheLevel := (eax >> 5) & 7
|
||
coherency := int(ebx&0xfff) + 1
|
||
partitions := int((ebx>>12)&0x3ff) + 1
|
||
associativity := int((ebx>>22)&0x3ff) + 1
|
||
sets := int(ecx) + 1
|
||
size := associativity * partitions * coherency * sets
|
||
switch cacheLevel {
|
||
case 1:
|
||
if cacheType == 1 {
|
||
// 1 = Data Cache
|
||
c.Cache.L1D = size
|
||
} else if cacheType == 2 {
|
||
// 2 = Instruction Cache
|
||
c.Cache.L1I = size
|
||
} else {
|
||
if c.Cache.L1D < 0 {
|
||
c.Cache.L1I = size
|
||
}
|
||
if c.Cache.L1I < 0 {
|
||
c.Cache.L1I = size
|
||
}
|
||
}
|
||
case 2:
|
||
c.Cache.L2 = size
|
||
case 3:
|
||
c.Cache.L3 = size
|
||
}
|
||
}
|
||
case AMD, Hygon:
|
||
// Untested.
|
||
if maxExtendedFunction() < 0x80000005 {
|
||
return
|
||
}
|
||
_, _, ecx, edx := cpuid(0x80000005)
|
||
c.Cache.L1D = int(((ecx >> 24) & 0xFF) * 1024)
|
||
c.Cache.L1I = int(((edx >> 24) & 0xFF) * 1024)
|
||
|
||
if maxExtendedFunction() < 0x80000006 {
|
||
return
|
||
}
|
||
_, _, ecx, _ = cpuid(0x80000006)
|
||
c.Cache.L2 = int(((ecx >> 16) & 0xFFFF) * 1024)
|
||
|
||
// CPUID Fn8000_001D_EAX_x[N:0] Cache Properties
|
||
if maxExtendedFunction() < 0x8000001D {
|
||
return
|
||
}
|
||
for i := uint32(0); i < math.MaxUint32; i++ {
|
||
eax, ebx, ecx, _ := cpuidex(0x8000001D, i)
|
||
|
||
level := (eax >> 5) & 7
|
||
cacheNumSets := ecx + 1
|
||
cacheLineSize := 1 + (ebx & 2047)
|
||
cachePhysPartitions := 1 + ((ebx >> 12) & 511)
|
||
cacheNumWays := 1 + ((ebx >> 22) & 511)
|
||
|
||
typ := eax & 15
|
||
size := int(cacheNumSets * cacheLineSize * cachePhysPartitions * cacheNumWays)
|
||
if typ == 0 {
|
||
return
|
||
}
|
||
|
||
switch level {
|
||
case 1:
|
||
switch typ {
|
||
case 1:
|
||
// Data cache
|
||
c.Cache.L1D = size
|
||
case 2:
|
||
// Inst cache
|
||
c.Cache.L1I = size
|
||
default:
|
||
if c.Cache.L1D < 0 {
|
||
c.Cache.L1I = size
|
||
}
|
||
if c.Cache.L1I < 0 {
|
||
c.Cache.L1I = size
|
||
}
|
||
}
|
||
case 2:
|
||
c.Cache.L2 = size
|
||
case 3:
|
||
c.Cache.L3 = size
|
||
}
|
||
}
|
||
}
|
||
|
||
return
|
||
}
|
||
|
||
type SGXEPCSection struct {
|
||
BaseAddress uint64
|
||
EPCSize uint64
|
||
}
|
||
|
||
type SGXSupport struct {
|
||
Available bool
|
||
LaunchControl bool
|
||
SGX1Supported bool
|
||
SGX2Supported bool
|
||
MaxEnclaveSizeNot64 int64
|
||
MaxEnclaveSize64 int64
|
||
EPCSections []SGXEPCSection
|
||
}
|
||
|
||
func hasSGX(available, lc bool) (rval SGXSupport) {
|
||
rval.Available = available
|
||
|
||
if !available {
|
||
return
|
||
}
|
||
|
||
rval.LaunchControl = lc
|
||
|
||
a, _, _, d := cpuidex(0x12, 0)
|
||
rval.SGX1Supported = a&0x01 != 0
|
||
rval.SGX2Supported = a&0x02 != 0
|
||
rval.MaxEnclaveSizeNot64 = 1 << (d & 0xFF) // pow 2
|
||
rval.MaxEnclaveSize64 = 1 << ((d >> 8) & 0xFF) // pow 2
|
||
rval.EPCSections = make([]SGXEPCSection, 0)
|
||
|
||
for subleaf := uint32(2); subleaf < 2+8; subleaf++ {
|
||
eax, ebx, ecx, edx := cpuidex(0x12, subleaf)
|
||
leafType := eax & 0xf
|
||
|
||
if leafType == 0 {
|
||
// Invalid subleaf, stop iterating
|
||
break
|
||
} else if leafType == 1 {
|
||
// EPC Section subleaf
|
||
baseAddress := uint64(eax&0xfffff000) + (uint64(ebx&0x000fffff) << 32)
|
||
size := uint64(ecx&0xfffff000) + (uint64(edx&0x000fffff) << 32)
|
||
|
||
section := SGXEPCSection{BaseAddress: baseAddress, EPCSize: size}
|
||
rval.EPCSections = append(rval.EPCSections, section)
|
||
}
|
||
}
|
||
|
||
return
|
||
}
|
||
|
||
func support() flagSet {
|
||
var fs flagSet
|
||
mfi := maxFunctionID()
|
||
vend, _ := vendorID()
|
||
if mfi < 0x1 {
|
||
return fs
|
||
}
|
||
family, model := familyModel()
|
||
|
||
_, _, c, d := cpuid(1)
|
||
fs.setIf((d&(1<<15)) != 0, CMOV)
|
||
fs.setIf((d&(1<<23)) != 0, MMX)
|
||
fs.setIf((d&(1<<25)) != 0, MMXEXT)
|
||
fs.setIf((d&(1<<25)) != 0, SSE)
|
||
fs.setIf((d&(1<<26)) != 0, SSE2)
|
||
fs.setIf((c&1) != 0, SSE3)
|
||
fs.setIf((c&(1<<5)) != 0, VMX)
|
||
fs.setIf((c&0x00000200) != 0, SSSE3)
|
||
fs.setIf((c&0x00080000) != 0, SSE4)
|
||
fs.setIf((c&0x00100000) != 0, SSE42)
|
||
fs.setIf((c&(1<<25)) != 0, AESNI)
|
||
fs.setIf((c&(1<<1)) != 0, CLMUL)
|
||
fs.setIf(c&(1<<23) != 0, POPCNT)
|
||
fs.setIf(c&(1<<30) != 0, RDRAND)
|
||
|
||
// This bit has been reserved by Intel & AMD for use by hypervisors,
|
||
// and indicates the presence of a hypervisor.
|
||
fs.setIf(c&(1<<31) != 0, HYPERVISOR)
|
||
fs.setIf(c&(1<<29) != 0, F16C)
|
||
fs.setIf(c&(1<<13) != 0, CX16)
|
||
|
||
if vend == Intel && (d&(1<<28)) != 0 && mfi >= 4 {
|
||
fs.setIf(threadsPerCore() > 1, HTT)
|
||
}
|
||
if vend == AMD && (d&(1<<28)) != 0 && mfi >= 4 {
|
||
fs.setIf(threadsPerCore() > 1, HTT)
|
||
}
|
||
// Check XGETBV/XSAVE (26), OXSAVE (27) and AVX (28) bits
|
||
const avxCheck = 1<<26 | 1<<27 | 1<<28
|
||
if c&avxCheck == avxCheck {
|
||
// Check for OS support
|
||
eax, _ := xgetbv(0)
|
||
if (eax & 0x6) == 0x6 {
|
||
fs.set(AVX)
|
||
switch vend {
|
||
case Intel:
|
||
// Older than Haswell.
|
||
fs.setIf(family == 6 && model < 60, AVXSLOW)
|
||
case AMD:
|
||
// Older than Zen 2
|
||
fs.setIf(family < 23 || (family == 23 && model < 49), AVXSLOW)
|
||
}
|
||
}
|
||
}
|
||
// FMA3 can be used with SSE registers, so no OS support is strictly needed.
|
||
// fma3 and OSXSAVE needed.
|
||
const fma3Check = 1<<12 | 1<<27
|
||
fs.setIf(c&fma3Check == fma3Check, FMA3)
|
||
|
||
// Check AVX2, AVX2 requires OS support, but BMI1/2 don't.
|
||
if mfi >= 7 {
|
||
_, ebx, ecx, edx := cpuidex(7, 0)
|
||
eax1, _, _, _ := cpuidex(7, 1)
|
||
if fs.inSet(AVX) && (ebx&0x00000020) != 0 {
|
||
fs.set(AVX2)
|
||
}
|
||
// CPUID.(EAX=7, ECX=0).EBX
|
||
if (ebx & 0x00000008) != 0 {
|
||
fs.set(BMI1)
|
||
fs.setIf((ebx&0x00000100) != 0, BMI2)
|
||
}
|
||
fs.setIf(ebx&(1<<2) != 0, SGX)
|
||
fs.setIf(ebx&(1<<4) != 0, HLE)
|
||
fs.setIf(ebx&(1<<9) != 0, ERMS)
|
||
fs.setIf(ebx&(1<<11) != 0, RTM)
|
||
fs.setIf(ebx&(1<<14) != 0, MPX)
|
||
fs.setIf(ebx&(1<<18) != 0, RDSEED)
|
||
fs.setIf(ebx&(1<<19) != 0, ADX)
|
||
fs.setIf(ebx&(1<<29) != 0, SHA)
|
||
// CPUID.(EAX=7, ECX=0).ECX
|
||
fs.setIf(ecx&(1<<5) != 0, WAITPKG)
|
||
fs.setIf(ecx&(1<<25) != 0, CLDEMOTE)
|
||
fs.setIf(ecx&(1<<27) != 0, MOVDIRI)
|
||
fs.setIf(ecx&(1<<28) != 0, MOVDIR64B)
|
||
fs.setIf(ecx&(1<<29) != 0, ENQCMD)
|
||
fs.setIf(ecx&(1<<30) != 0, SGXLC)
|
||
// CPUID.(EAX=7, ECX=0).EDX
|
||
fs.setIf(edx&(1<<11) != 0, RTM_ALWAYS_ABORT)
|
||
fs.setIf(edx&(1<<14) != 0, SERIALIZE)
|
||
fs.setIf(edx&(1<<16) != 0, TSXLDTRK)
|
||
fs.setIf(edx&(1<<26) != 0, IBPB)
|
||
fs.setIf(edx&(1<<27) != 0, STIBP)
|
||
|
||
// Only detect AVX-512 features if XGETBV is supported
|
||
if c&((1<<26)|(1<<27)) == (1<<26)|(1<<27) {
|
||
// Check for OS support
|
||
eax, _ := xgetbv(0)
|
||
|
||
// Verify that XCR0[7:5] = ‘111b’ (OPMASK state, upper 256-bit of ZMM0-ZMM15 and
|
||
// ZMM16-ZMM31 state are enabled by OS)
|
||
/// and that XCR0[2:1] = ‘11b’ (XMM state and YMM state are enabled by OS).
|
||
hasAVX512 := (eax>>5)&7 == 7 && (eax>>1)&3 == 3
|
||
if runtime.GOOS == "darwin" {
|
||
hasAVX512 = fs.inSet(AVX) && darwinHasAVX512()
|
||
}
|
||
if hasAVX512 {
|
||
fs.setIf(ebx&(1<<16) != 0, AVX512F)
|
||
fs.setIf(ebx&(1<<17) != 0, AVX512DQ)
|
||
fs.setIf(ebx&(1<<21) != 0, AVX512IFMA)
|
||
fs.setIf(ebx&(1<<26) != 0, AVX512PF)
|
||
fs.setIf(ebx&(1<<27) != 0, AVX512ER)
|
||
fs.setIf(ebx&(1<<28) != 0, AVX512CD)
|
||
fs.setIf(ebx&(1<<30) != 0, AVX512BW)
|
||
fs.setIf(ebx&(1<<31) != 0, AVX512VL)
|
||
// ecx
|
||
fs.setIf(ecx&(1<<1) != 0, AVX512VBMI)
|
||
fs.setIf(ecx&(1<<6) != 0, AVX512VBMI2)
|
||
fs.setIf(ecx&(1<<8) != 0, GFNI)
|
||
fs.setIf(ecx&(1<<9) != 0, VAES)
|
||
fs.setIf(ecx&(1<<10) != 0, VPCLMULQDQ)
|
||
fs.setIf(ecx&(1<<11) != 0, AVX512VNNI)
|
||
fs.setIf(ecx&(1<<12) != 0, AVX512BITALG)
|
||
fs.setIf(ecx&(1<<14) != 0, AVX512VPOPCNTDQ)
|
||
// edx
|
||
fs.setIf(edx&(1<<8) != 0, AVX512VP2INTERSECT)
|
||
fs.setIf(edx&(1<<22) != 0, AMXBF16)
|
||
fs.setIf(edx&(1<<24) != 0, AMXTILE)
|
||
fs.setIf(edx&(1<<25) != 0, AMXINT8)
|
||
// eax1 = CPUID.(EAX=7, ECX=1).EAX
|
||
fs.setIf(eax1&(1<<5) != 0, AVX512BF16)
|
||
}
|
||
}
|
||
}
|
||
|
||
if maxExtendedFunction() >= 0x80000001 {
|
||
_, _, c, d := cpuid(0x80000001)
|
||
if (c & (1 << 5)) != 0 {
|
||
fs.set(LZCNT)
|
||
fs.set(POPCNT)
|
||
}
|
||
fs.setIf((c&(1<<10)) != 0, IBS)
|
||
fs.setIf((d&(1<<31)) != 0, AMD3DNOW)
|
||
fs.setIf((d&(1<<30)) != 0, AMD3DNOWEXT)
|
||
fs.setIf((d&(1<<23)) != 0, MMX)
|
||
fs.setIf((d&(1<<22)) != 0, MMXEXT)
|
||
fs.setIf((c&(1<<6)) != 0, SSE4A)
|
||
fs.setIf(d&(1<<20) != 0, NX)
|
||
fs.setIf(d&(1<<27) != 0, RDTSCP)
|
||
|
||
/* XOP and FMA4 use the AVX instruction coding scheme, so they can't be
|
||
* used unless the OS has AVX support. */
|
||
if fs.inSet(AVX) {
|
||
fs.setIf((c&0x00000800) != 0, XOP)
|
||
fs.setIf((c&0x00010000) != 0, FMA4)
|
||
}
|
||
|
||
}
|
||
if maxExtendedFunction() >= 0x80000007 {
|
||
_, b, _, d := cpuid(0x80000007)
|
||
fs.setIf((b&(1<<0)) != 0, MCAOVERFLOW)
|
||
fs.setIf((b&(1<<1)) != 0, SUCCOR)
|
||
fs.setIf((b&(1<<2)) != 0, HWA)
|
||
fs.setIf((d&(1<<9)) != 0, CPBOOST)
|
||
}
|
||
|
||
if maxExtendedFunction() >= 0x80000008 {
|
||
_, b, _, _ := cpuid(0x80000008)
|
||
fs.setIf((b&(1<<9)) != 0, WBNOINVD)
|
||
fs.setIf((b&(1<<8)) != 0, MCOMMIT)
|
||
fs.setIf((b&(1<<13)) != 0, INT_WBINVD)
|
||
fs.setIf((b&(1<<4)) != 0, RDPRU)
|
||
fs.setIf((b&(1<<3)) != 0, INVLPGB)
|
||
fs.setIf((b&(1<<1)) != 0, MSRIRC)
|
||
fs.setIf((b&(1<<0)) != 0, CLZERO)
|
||
}
|
||
|
||
if maxExtendedFunction() >= 0x8000001b && fs.inSet(IBS) {
|
||
eax, _, _, _ := cpuid(0x8000001b)
|
||
fs.setIf((eax>>0)&1 == 1, IBSFFV)
|
||
fs.setIf((eax>>1)&1 == 1, IBSFETCHSAM)
|
||
fs.setIf((eax>>2)&1 == 1, IBSOPSAM)
|
||
fs.setIf((eax>>3)&1 == 1, IBSRDWROPCNT)
|
||
fs.setIf((eax>>4)&1 == 1, IBSOPCNT)
|
||
fs.setIf((eax>>5)&1 == 1, IBSBRNTRGT)
|
||
fs.setIf((eax>>6)&1 == 1, IBSOPCNTEXT)
|
||
fs.setIf((eax>>7)&1 == 1, IBSRIPINVALIDCHK)
|
||
}
|
||
|
||
return fs
|
||
}
|
||
|
||
func valAsString(values ...uint32) []byte {
|
||
r := make([]byte, 4*len(values))
|
||
for i, v := range values {
|
||
dst := r[i*4:]
|
||
dst[0] = byte(v & 0xff)
|
||
dst[1] = byte((v >> 8) & 0xff)
|
||
dst[2] = byte((v >> 16) & 0xff)
|
||
dst[3] = byte((v >> 24) & 0xff)
|
||
switch {
|
||
case dst[0] == 0:
|
||
return r[:i*4]
|
||
case dst[1] == 0:
|
||
return r[:i*4+1]
|
||
case dst[2] == 0:
|
||
return r[:i*4+2]
|
||
case dst[3] == 0:
|
||
return r[:i*4+3]
|
||
}
|
||
}
|
||
return r
|
||
}
|